Center for Manycore Programming

Configuring FaCSim

You can configure some of the details of FaCSim by editing the system configuration file. A sample configuration file (facsim.config) can be found in the bin directory under the FaCSim distribution directory. The sample configuration file is for Versatile AB evaluation board from ARM. The configuration file consists of four sections.

1. Core

This section specifies the type of processor core (core_type) and its frequency (frequency) in MHz. The simulated system that is configured by the following configuration has an ARM9E core that operates with the core clock frequency, 140 MHz.

### core_type, frequency (MHz)
CORE: ARM9E, 140

Currently FaCSim supports only the ARM9E core.

2. Bus

This section configures the bus architecture of the simulated system. Currently, FaCSim supports only the AHB bus architecture. The AHB specification can be found http://www.arm.com/products/system-ip/amba-specifications.php. You can configure the ratio of core frequency to bus frequency (ratio of core frequency to bus frequency).

### Latency in bus cycles
### bus_type, ratio of core frequency to bus frequency
BUS: AHB, 3

3. Memory Subsystem

This section configures all the components in the memory subsystem. Currently, FaCSim supports all the memory subsystem components of the ARM926EJ-S processor. The details about the memory subsystem of ARM926EJ-S can be found in http://www.arm.com/products/processors/classic/arm9/arm926.php. The memory subsystem section begins with,

### Memory subsystem - begin
MEMORY_SUBSYSTEM {

And, it ends with,

### Memory subsystem - end
}

You can either enable or disable each component in the memory subsystem with on and off. Of course, your application can dynamically enable or disable them by modifying CP15 coprocessor registers.

The latencies of some components, such as micro-TLBs and TLB, need to be represented in a unit of centi-cycle, which is 100 times finer than a core clock cycle.

3.1. Main Write Buffer

You can configure the hit latency (latency) of the main write buffer in core cycles.

### Latency in core cycles
### on/off, latency
  MAIN WRITE BUFFER: on, 1

3.2. Micro TLBs

You can configure both micro-TLBs ( instruction-side (IMICROTLB) and data-side (DMICROTLB)) by providing the number of entries (num_entries) in the micro-TLB, the access latency of a single entry (latency), and the latency for invalidating all entries (latency_inv_all). All the latencies of the micro TLBs are in centi-cycles.

### Latency in centi-cycles
### on/off, num_entries, latency, latency_inv_all
  IMICROTLB: off, 8, 40, 160
  DMICROTLB: off, 8, 40, 160

3.3. TLB

You can configure the TLB by providing its number of entries (num_entries), associtivity (assoc), access latency (latency), and latency for invalidating all entries (latency_inv_all). All the latencies of the TLB are in centi-cycles.

### Latency in centi-cycles
### on/off, num_entries, assoc, latency, latency_inv_all
  TLB: off, 64, 2, 60, 2560

3.4. Memory Management Unit (MMU)

You can configure the MMU by providing its latency for a normal request (latency) in centi-cycles. The latency does not include the memory access latency for the MMU's page table walk.

### Latency in centi-cycles
### on/off, latency
  MMU: off, 100

3.5. Instruction Cache

You can configure the instruction cache by providing its size (size), hit latency (latency), and latency for invalidating all entries (latency_inv_all). The latencies are in core clock cycles, and the size of instruction cache is in Kilo-Bytes.

### Latency in core cycles 
### ARM926 ICache
  ### Associativity = 4
  ### Line size = 32B
  ###
  ### on/off, size(KB), latency, latency_inv_all
  ICACHE: off, 32, 1, 100

3.6. Data Cache

You can configure the data cache by providing its size (size), hit latency (latency), latency for invalidating all entries (latency_inv_all), latency for cleaning all entries (latency_clean_all), and latency of write-back buffer (wbb_latency). The latencies are in core cycles, and the size of the data cache is in Kilo-Bytes.

### Latency in core cycles
### ARM926 DCache
  ### Associativity = 4
  ### Line size = 32B
  ### Number of dirty bits = 2
  ###
  ### on/off, size(KB), latency, latency_inv_all, latency_clean_all, 
  ### wbb_on/off, wbb_latency
  DCACHE: off, 32, 1, 100, 100, on, 1

3.7. Tightly Coupled Memory (TCM)

You can configure both of the instruction side (ITCM) and data side (DTCM) TCMs by providing their base address (base address), size (size), and access latency (latency). The latencies are in core cycles and the size of the TCM is in Kilo-Bytes.

### Latency in core cycles
  ### on/off, base address, size(KB), latency
  ITCM: off, 0x0, 32, 2
  DTCM: off, 0x01000000, 32, 2

3.8. Instruction Prefetch Buffer (IPB)

You can configure the IPB by providing its access latency (latency). The latency is in core cycles.

### Latency in core cycles
  ### on/off, latency
  IPB: on, 1

3.9. Memory Regions

You can configure different external memory regions, such as SDRAM and memory mapped I/O devices. Each region is configured in its own format. Since the FaCSim component for each region is provided as a shared library object, the file name of the shared object (SO_NAME) for each region needs to be specified first. The configuration bellow is for ARM PrimeCell Timer Module (TMRS804) and ARM PrimeCell MultiPort Memory Controller (MPMCGX175).

MEMORY_REGIONS
  {
    ###NAME: TYPE { SO_NAME, BASE, SIZE(KB), CLOCK(KHZ), IRQ_NO }
    TIMER01: TMRSP804 { timersp804.so, 0x101E2000, 4, 32, 4 }

    ###NAME: TYPE { SO_NAME, BASE1, SIZE1, BASE2, SIZE2,
                    ### #_of_bank_bits, #_of_row_bits, #_of_column_bits,
                    ### NS_read_hit, NS_read_miss, S_read,
                    ### NS_write_hit, NS_write_miss, S_write }
    MPMC: MPMCGX175 { mpmcgx175.so, 0x00000000, 0x20000, 0x10110000, 64,
                      2, 13, 10,
                      9, 11, 1,
                      4, 10, 1 }
  }

You can configure the SP804 timer module by providing its address range (BASE and SIZE), clock frequency (CLOCK), and interrupt request number (IRQ_NO). The size of the address range is in Kilo-Bytes.

MPMC is an SDRAM controller. FaCSim checks whether an external memory request is a row buffer hit or not in the SDRAM with MPMC. Since MPMC has many registers that contain the information about the SDRAM, MPMC requires two address ranges: one for the SDRAM (BASE1, SIZE1) and the other for its control registers (BASE2, SIZE2). The sizes of the address ranges are in Bytes.

You can specify the bank configuration of the SDRAM by modifying the number of bits (#_of_bank_bits) that represents the number of SDRAM banks, the number of bits (#_of_row_bits) that represents the number of rows, and the number of bits (#_of_column_bits) that represents the number of columns. The memory controller configuration below tells that the SDRAM consists of 4 banks (#_of_bank_bits : 2). Each bank consists of 8096 rows (#_of_row_bits : 13), and the size of each row is 1024 words (#_of_column_bit : 10). The remaining numbers are the SDRAM latencies in bus cycles. NS_(read/write)_(hit/miss) is the latency of a non-sequential read/write request when it is a row-buffer miss/hit. S_(read/write) is the latency of a sequential read/write request.